The present filing is related to filing TI-35840 xe2x80x9cGeometry-Controllable Design Blocks of MOS Transistors for Improved ESD Protectionxe2x80x9d.
1. Field of the Invention
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the layout of multi-finger MOS transistors aiming at ESD protection.
2. Description of the Related Art
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the human body (described by the xe2x80x9cHuman Body Modelxe2x80x9d, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (described by the Machine modelxe2x80x9d, MM); it can generate transients with significantly higher rise times and current levels than the HBM ESD source. A third source is described by the xe2x80x9ccharged device modelxe2x80x9d (CDM), in which the IC itself becomes charged and discharges to ground in rise times less than 500 ps.
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fieldsxe2x80x94all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
It is well known that for non-silicided or silicide-blocked nMOS transistors, the second breakdown trigger current (It2), which is widely used as an ESD strength monitor, can be increased with larger drain contact spacings because of more uniform triggering of the lateral npn structure, due to ballast resistance effects. In addition, it is also well established that effectiveness is much reduced in the case of devices with silicided diffusions, since the ballast resistance is insufficient, making the devices susceptible to current localization, which leads to early ESD failure. In silicided cMOS devices, the primary cause of the degradation of ESD failure threshold is known to be non-uniform bipolar conduction, which is attributed to insufficient ballasting resistance in the fully silicided source/drain structures. This decrease in ESD strength imposes severe restrictions on the efficient design of ESD protection. Known options for correcting this shortcoming either require an extra mask or more process complexity, resulting in increased process cost and chip real estate.
An urgent need has therefore arisen for cost effective design methods to achieve advanced ESD protection, compatible with uniform turn-on, high response speed, low capacitance and low leakage current using standard CMOS processing. The device structures should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
One embodiment of the invention is an MOS transistor in the surface of a semiconductor substrate of a first conductivity type, which has a grid of isolations in the surface, each grid unit surrounding a rectangular substrate island. Each island contains two parallel regions of the opposite conductivity type: one region is operable as the transistor drain and the other region is operable as the transistor drain, each region abutting the isolation. A transistor gate is between the parallel regions, completing the formation of a transistor. Electrical contacts are placed on the source region so that the spacing between each contact and the adjacent isolation is at least twice as large as the spacing between each contact and the gate. A plurality of these islands is interconnected to form a multi-finger MOS transistor. The source contact spacings are selected to increase the failure threshold current of the multi-finger MOS transistor by spreading the power dissipation and thus reducing the current localization, whereby the protection of the transistor against ESD pulses is improved.
Another embodiment of the invention has also the drain contacts placed so that the spacing between each contact and the adjacent isolation is at least twice as large as the spacing between each contact and the gate.
Embodiments of the present invention are related to advanced deep submicron technology devices with shallow trench isolation, especially salicided nMOS transistors. Such transistors are for instance employed in wireless devices, or in Application Specific products, or in mixed signal and logic devices.
A technical advantage of the invention is its simplicity so that it can easily be adopted into any integrated circuit design methodology.
Another technical advantage of the invention is that it may be implemented using standard semiconductor processing techniques. For ESD protection circuitry, as well as for general equalization needs, no additional processing time or expense to the integrated circuit is needed.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.